Services

DFT Consulting

• Expert in All Major EDA DFT Vendors
• Senior DFT Engineers
• World-Wide Support
• DFT Architecture
• DFT RTL Development
• Scan Compression
• Stuck-AT, Transition, Path Delay, IDDQ, Cell-Aware
• Fault Diagnostics and Analysis/Identification
• Root Cause failure identification
• DFT Gate & RTL Level Simulation/Verification
• Embedded IP Testing – ARM, DDR, Memory, Serdes, more…
• Expert in IEEE Standards (1149.1, 1149.6, 1687, 1500, 1838)
• IJTAG – Automated and Custom consulting services
• Post Silicon Support
• DFT Related Timing Constraints

Initial Phases

• DFT Evaluation & Assessment
• DFT Methodology Development
• DFT Automatio
• Design Vs Test Time
• ATPG Library Generation including Cell-Aware

Implementation

• Scan Insertion
• Add / Optimize Test Control Logic
• ATPG Vector Generation
• Memory BIST
• Logic BIST
• JTAG Generation
• Fault Simulation & Grading
• Manufacturing Test Program Debug
• Failure Analysis Assistance

Education

• DFT Classes & Educational Services